Recently, as a method for producing an SOI wafer, the method comprising bonding a wafer implanted with hydrogen ions or the like and then delaminating the wafer to produce an SOI wafer (a technique called hydrogen ion delamination method: Smart Cut Method (registered trademark)) is newly coming to attract much attention. This method is a technique for producing an SOI wafer, wherein an oxide layer is formed on at least one of two silicon wafers, at least either hydrogen ions or rare gas ions are implanted into one wafer from its top surface to form a micro bubble layer (enclosed layer) in this silicon wafer, then the ion-implanted surface of the wafer is bonded to the other silicon wafer via the oxide layer, thereafter the wafers were subjected to a heat treatment (delamination heat treatment) to delaminate one of the wafer as a thin film at the micro bubble layer as a cleavage plane, and the other wafer is further subjected to a heat treatment (bonding heat treatment) to obtain an SOI wafer in which an SOI layer is firmly bonded on the silicon wafer (refer to Japanese Patent Laid-open (Kokai) Publication No. 5-211128).
When an SOI wafer is produced by the hydrogen ion delamination method, the SOI layer surface as it is after the delamination at the micro bubble layer as a cleavage plane has higher surface roughness compared with a mirror-polished wafer used for usual device production, and therefore the wafer as it is cannot be used for the device production. Accordingly, in order to improve the aforementioned surface roughness, polishing using a small amount of stock removal for polishing, which is called touch polish, is usually performed.
However, the SOI layer is extremely thin, and therefore when its surface is polished, there is caused a problem that variation in SOI layer thickness becomes large due to fluctuation of the polishing amount within the surface.
Therefore, it was proposed to improve the surface roughness by a heat treatment of the SOI layer surface immediately after the delamination, without using polishing.
Japanese Patent Laid-open (Kokai) Publication No. 10-242154 discloses a method wherein, after a second heat treatment for strengthening bonding of a support substrate and a single crystal silicon thin film (bonding heat treatment), a third heat treatment is performed at a temperature of 1000–1300° C. for 10 minutes to 5 hours in a hydrogen atmosphere to improve average surface roughness of the silicon thin film.
Further, Japanese Patent Laid-open (Kokai) Publication No. 10-275905 discloses a method for producing an SOI wafer wherein a wafer of the SOI structure having a delaminated surface, which is obtained by the hydrogen ion delamination method, is subjected to annealing in a hydrogen atmosphere (hydrogen annealing) to flatten the delaminated surface.
Thus, any of the techniques disclosed in the aforementioned patent documents utilizes a heat treatment in a hydrogen atmosphere to improve the surface roughness of a delaminated wafer.
The aforementioned Japanese Patent Laid-open (Kokai) Publication No. 10-242154 defines temperature and time for the third heat treatment (hydrogen annealing) for improving the average surface roughness. However, if, for example, the SOI layer (single crystal silicon thin film) is formed from a wafer produced by the Czochralski method (CZ method) and it has a small thickness of about 0.5 μm or less, there is caused a problem that a buried oxide layer is etched by hydrogen gas penetrated through COP (Crystal Originated Particle), which is a void-like grown-in defect, when the hydrogen annealing is performed. Further, although it is known that a heat treatment performed in an argon atmosphere also improves the surface roughness like the heat treatment in hydrogen, however, it also cannot obviate the problem of etching through COP. That is, it is known that a CZ wafer has crystal defects called COPs introduced therein during the crystal growth, and it has become clear that, if such a CZ wafer is utilized for the bond wafer to be a device active layer, COPs exist also in the SOI layer and in a case of an extremely thin SOI layer, which is required in recent years, the COPs penetrate the SOI layer and form pinholes to markedly degrade electric characteristics.
Meanwhile, Japanese Patent Laid-open (Kokai) Publication No. 10-275905 discloses that, as specific methods for the heat treatment (annealing), the heat treatment can be performed by any one of short time annealing (rapid thermal anneal, RTA) of the single wafer processing in which wafer is treated one by one and plasma annealing, besides the method of hydrogen annealing performed for several tens of seconds to several tens of minutes in a hydrogen atmosphere using a batch processing type furnace.
Among the aforementioned various heat treatments (annealing), the rapid thermal annealing (RTA) utilizing a rapid heating/rapid cooling apparatus can be performed within an extremely short period of time. Therefore, it was considered that the aforementioned buried oxide layer was not etched, COPs in the SOI layer could be eliminated simultaneously, and thus the surface roughness could be improved efficiently.
However, when the inventors of the present invention precisely investigated the improvement of the surface roughness of SOI wafer by RTA, it was found that it was only short period components of surface roughness that were improved to a level comparable to that of mirror-polished wafers for the usual device production, and long period components were still extremely inferior to those of the mirror-polished wafers.
When the relationship between the heat treatment time and the surface roughness was further investigated, it was found that, in order to improve the long period components of surface roughness by an RTA apparatus, a heat treatment of high temperature for long period of time (for example, at 1225° C. for 3 hours or more) was required.
However, since the heat treatment performed by an RTA apparatus is one of the single wafer processing type, treatment for a long period of time lowers throughput and degrades efficiency. In addition, it increases the production cost. Therefore, it is not practical.
On the other hand, although a batch processing furnace that enables a heat treatment for a long period of time can treat a lot of wafers at one time, it suffers from a problem that the buried oxide layer is etched through COPs in the SOI layer during the hydrogen annealing treatment to form pits due to the slower temperature increasing rate.